HP-HIL

Cable and connectors

Side-clamps, similar to some IBM cash register plugs
Plug body appears to be similar to a plastic or metal ‘RJ-‘ style plug
Devices and cables had one or two dots; some devices had one ‘one dot’ port and one ‘two dot’ port; this probably referred to different ends of the same cables (i.e. they were ~not~ ‘crossover’ cables) - they may also be ‘keyed’ differently (uses ‘E’ keying for downstream jacks, ‘A’ keying for upstream jacks; i.e. a mouse would have an attached cable with a single male ‘E’ keyed connector)
Provides bus power to devices (current limit??)

Devices regulate their own 5VDC power from the 12V (+/- 5%) bus power
Typical devices originally required 100 mA; system host should provide 750 mA minimum (some early devices used 150 mA or more)
Minimum voltage to devices should be 7.3V to support all 5V voltage regulators
Devices should function with input voltage from 7.3V–12.6 VDC
Bypass 12V at connector with both 0.01 and 25 microfarad capacitors
Limit total link power (to what?; schematic uses 5A fuse, implying a nominal 60W; 14W might be the max expected in worst-case scenarios, ~not~ including losses due to cable resistance - jhg; max available current of 8A recommended) for safety
Devices can exceed printed current ratings by 10% max

Up to seven total external devices, not including the host device
Max resistance 0.8 ohms per line, including connectors; max 0.4 ohms shield resistance, including plug shells; 100 megohm min insulation resistance; max capacitance between signal line and any other cable part 600 pF (with other conductors and shield shorted connected); dielectric resistance minimum 1500 VRMS

Note: shield is separate from ground in devices; routed back to host for ESD suppression and RFI minimization

15 bits (start, stop, command, parity, address, and data bits)
Always originate from host, except for device-initiated hard reset commands
Data returned by a device is appended with the requesting command, so host knows transmission is complete
Data rate approximately 10 microseconds / bit +/- 0.5% (about 150 microseconds / frame)
Start bit: logic 0
Stop bit: logic 1
Minimum idle time between frames: 4 microseconds
Max transmission rate 1 frame / 154 microseconds
Max throughput 6500 bytes/second
Parity is odd (based on all 15 bits)

Frame layout:

Bit 0: start (always logic 0)
Bit 1-3: address (3 bit; 7 possible devices + 0 for initialization / ‘all stations’ commands)
Bit 4: command bit
Bit 5-12: Opcode/data byte
Bit 13: parity bit
Bit 14: stop bit (always logic 1)

MLC: Master Link Controller; HP IC for host; contains 16 frame FIFO buffer; allows automatic device polling; allows devices to reset host processor

SLC: Slave Link Controller; HP IC for devices; retransmits data; clock generation for device processors; device processor handles link protocol

HP 46089A 4-Button Cursor (used mini-DIN style connector; not sure if was HP-HIL)

NMI

Non-Maskable Interrupt

Used for ‘hard reset’ of host from HMI devices

Shielded Data Link

Not standard AMP connectors, due to stronger keying ridges and color-coding (white for ‘A’-keyed receptacles and black for ‘E’-keyed receptacles)

AMP part numbers:

‘A’ keying, white, female SDL: 1-520792-1

‘E’ keying, black, female SDL: 5-520791-1

‘A’ keying, clear, male SDL:

‘E” keying, smoke, male SDL: